1. Field of the Invention
The present invention relates to interconnection technologies within semiconductor chips, especially to semiconductor devices with Through-Silicon-Via (TSV).
2. Description of the Prior Art
Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components. For the most part, this improvement in integration density has come from repeated reductions in the minimum feature size, allowing more components to be integrated into chips.
One method of scaling down includes three-dimensional stacking of chips used to form a stacked integrated circuit package. Three-dimensional (3-D) die stacking increases integration density and chip functionality by vertically integrating two or more dice. 3-D integration also improves interconnect speed by decreasing interconnect wire length, and reduces power dissipation and crosstalk.
Therefore, the Through-Silicon-Via (TSV) connection is developed to use in forming interconnects for stacked wafers, stacked chip, and/or combinations thereof for 3-D packaging technologies.
TSV is created through a substrate (e.g. wafer), by forming a via extending from a front surface to a back surface of the substrate, and filling the via with a conductive material. Generally the conductive material is copper.
Copper has a coefficients of thermal expansion (CTE) of approximately 16.5×10−6/K, and silicon has a CTE of approximately 4.68×10−6/K. Thus, this CTE mismatch may result in significant stress between the silicon and copper.
Because of the CTE mismatch, under normal operation, a mechanical stress may be induced at a copper-silicon interface when the package undergoes a temperature excursion. The stress may result in numerous problems, including thin-film delamination, cracking of the silicon and reduced transistor performance.
To maintain a mechanical stress resulting from a CTE mismatch for a given temperature excursion, via size may be reduced, spacing between adjacent vias may be increased, or vias may be positioned far from active circuitry. Each of these options may lead to increased chip size, lower density circuits or increased cost per chip.